1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an internal clock generation circuit for generating an internal clock in synchronization with a periodically supplied clock signal.
2. Description of the Background Art
Though an operating speed of a dynamic random access memory (DRAM) employed as a main memory in a system using a memory has been increased, it is still incomparable with that of a micro processor (MPU). It is one reason why an access time and a cycle time of a DRAM is often regarded as a bottle neck causing an overall system performance degradation. To avoid this problem, a Double Data Rate SDRAM (DDR SDRAM) which operates in synchronization with complementary clock signals has recently been proposed as a main memory for fast speed MPU.
In a specification proposed for the DDR SDRAM for allowing access time decrease, four consecutive data per one data input/output terminal, for example, are accessible at a fast speed in synchronization with complementary system clock signals (ext. CLK and ext. /CLK).
FIG. 20 illustrates waveforms showing an operation of the DDR SDRAM upon being accessed.
In this DDR SDRAM, eight-bit data (byte data) can be input/output through data input/output terminals DQ0-DQ7. FIG. 20 illustrates operations upon writing and reading of four consecutive data (8xc3x974=32 bits in total). The number of consecutively read data is called a burst length which is changeable by a mode register in the DDR SDRAM.
Operation mode is determined by a combination of states of external control signals /RAS, /CAS and /WE at an edge of the external clock signal ext. CLK. The combination of the states of the external control signals is usually called a command. Here, the external control signal /RAS is a row address strobe signal, the external control signal /CAS is a column address strobe signal and the external control signal /WE is a write enable signal. A signal Add. is an address signal supplied from an external source, a signal DQS is a data strobe signal indicating a timing of receiving/supplying of data and a signal D/Q is a data signal received/supplied via the data input/output terminal.
With reference to FIG. 20, at time t1, the external control signals /RAS, /CAS and /WE and the address signal Add. are taken in at a rising edge of the clock signal ext. CLK. The address signal Add. is supplied as a row address X and a column address Y multiplexed in a time divisional manner. At the rising edge of the clock signal ext. CLK at t1, if the external control signal /RAS is at an xe2x80x9cLxe2x80x9d (a logical low) which is an active state, an address signal Add. at the time is taken in as a row address Xa.
At time t2 at a rising edge of the clock signal ext. CLK, if the external control signal CAS is at xe2x80x9cLxe2x80x9d which is an active state, an address signal Add. at the time is taken in as a column address Yb.
The signals, that is, a command and the address signal are taken in at a rising edge of the ext. CLK. According to the taken row address Xa and column address Yb, a row and a column are selected in the DDR SDRAM.
When a predetermined clock period (3.5 clock cycles in FIG. 20) is elapsed at time t4 after the fall of the external control signal /RAS to xe2x80x9cLxe2x80x9d, first four data q0, q1, q2 and q3 are supplied as outputs from time t4 to t8. These four data are supplied in synchronization with cross points of the clock signal ext. CLK and the clock signal ext. /CLK.
To enable a fast data transfer, the data strobe signal DQS for notifying a timing of data receipt is supplied as an output in the same phase with the output data.
At time t3, overwrite (precharge) of a memory cell is performed, which is performed when the external control signals /RAS and /WE are at xe2x80x9cLxe2x80x9d at a rising edge of the clock signal ext. CLK.
A writing operation is illustrated from time t9 onward. A row address Xc is taken at the writing operation in the same manner as at the data reading.
At time t10, if the external control signals /CAS and /WE are both at xe2x80x9cLxe2x80x9d which is an active state at a rising edge of the clock signal ext. CLK, a column address Yd is taken in, and in addition, at time t11 currently supplied data d0 is taken in as a first write data.
In other words, in response to falls of external control signals /RAS and /CAS, a column and a row are selected in the DDR SDRAM. From time t12 to t14, input data d1, d2 and d3 are sequentially taken in synchronization with the data strobe signal DQS and written into the memory cells.
As described in the foregoing, in view of the overall system performance, as a speed of system clock increases along with the increase in the processing speed of MPU, the problem associated with the speed of internal clock signal (int. CLK) cannot be disregarded even in the DDR SDRAM. An internal clock generation circuit is proposed which employs a Delay Locked Loop (hereinafter referred to as DLL) for receiving a clock signal (ext. CLK) which is generated in a semiconductor device or supplied from an external source and generating an internal clock signal (int. CLK) in synchronization with the clock signal.
FIG. 21 is a block diagram showing a configuration of a conventional DLL circuit.
As shown in FIG. 21, the conventional DLL circuit includes a clock buffer B11 receiving an external clock signal ext. CLK supplied from an external source, a phase comparator B12 comparing a clock signal ECLK and a clock signal RCLK supplied from clock buffer B11 as outputs and supplying as an output control signals /UP and DOWN according to a phase difference, a charge pump B13 receiving the control signals /UP and DOWN, a loop filter B16 receiving an output from charge pump B13 and supplying as an output control voltage VCOin, a voltage controlling delay circuit B15 receiving the clock signal ECLK supplied as the output from clock buffer B11, delaying it according to control voltage VCOin and supplying as an output the resulting delayed clock ECLKxe2x80x2 and a clock buffer B14 receiving the delayed clock ECLKxe2x80x2 and supplying the clock signal RCLK and the internal clock signal int. CLK as outputs.
FIG. 22 is a circuit diagram showing a configuration of phase comparator B12 shown in FIG. 21.
With reference to FIG. 22, phase comparator B12 includes an inverter B12a receiving and inverting the clock signal ECLK, an NAND circuit B12f receiving an output of inverter B12a and a potential of a node Nl and having its output connected to a node Nf, an NAND circuit B121 having its inputs connected to nodes Nf, Nr and Ng and its output connected to node Nl, an NAND circuit B12g having its inputs connected to nodes Nf and Nh and its output connected to node Ng, an NAND circuit B12h having its inputs connected to nodes Ng and Nr and its output connected to node Nh and inverters B12c and B12d connected in series, having their input connected to the node Nl and supplying as an output the control signal /UP.
Phase comparator B12 further includes an inverter B12b receiving the clock signal RCLK, an NAND circuit B12k receiving an output of inverter B12b and a potential of a node Nn and having its output connected to a node Nk, an NAND circuit B12m having its inputs connected to nodes Nj, Nr and Nk and its output connected to node Nn, an NAND circuit B12j having its inputs connected to nodes Ni and Nk and its output connected to node Nj, an NAND circuit B12i having its inputs connected to nodes Nr and Nj and its output connected to node Ni, an NAND circuit B12n having its inputs connected to nodes Ng, Nf, Nk and Nj and its output connected to node Nr and an inverter B12e having its input connected to the node Nn and supplying as an output the control signal DOWN.
FIG. 23 is a circuit diagram showing a configuration of clock buffer B11 shown in FIG. 21.
With reference to FIG. 23, clock buffer B11, including m inverters Ia1-Iam (m is a natural number) connected in series, amplifies the external clock signal ext. CLK and supplies as an output the clock signal ECLK. Sizes of symbols of inverters Ia1-Iam represents load drivability of respective inverters, which gradually increase toward an output stage. The number of stages m of inverters Ia1-Iam is set according to input capacitance of phase comparator B12 and voltage controlling delay circuit B15.
FIG. 24 is a circuit diagram showing a configuration of clock buffer B14 shown in FIG. 21.
Next, with reference to FIG. 24, clock buffer B14 including n inverters Ib1-Ibn (n is a natural number) connected in series, amplifies the delayed clock ECLKxe2x80x2 supplied as the output from the voltage controlling delay circuit and supplies as outputs the internal clock signal int. CLK and the clock signal RCLK. The internal clock signal int. CLK is supplied to a control circuit section controlling each memory block.
Drivabilities of inverters Ib1-Ibn constituting clock buffer B14 also gradually increase toward an output stage as the inverters in clock buffer B11.
The number of stages n of inverters Ib1-Ibn is set according to an amount of load capacitance.
An inverter (Ib4 in FIG. 24) supplying as an output the clock signal RCLK is selected so that the phase difference between the external clock signal ext. CLK and the internal clock signal int. CLK becomes a predetermined amount.
FIG. 25 is a circuit diagram showing a configuration of charge pump B13 and loop filter B16 shown in FIG. 21.
With reference to FIG. 25, charge pump B13 includes a constant current source B13a, P channel MOS transistor B13b, an N channel MOS transistor B13c and a constant current source B13d connected in series between a power supply node to which power supply potential Vcc is applied and a ground node.
The gate of P channel MOS transistor B13b receives the control signal /UP whereas the gate of N channel MOS transistor B13c receives the control signal DOWN. A node N13 connecting P channel MOS transistor B13b and N channel MOS transistor B13c is an output node of charge pump B13.
Loop filter B16 includes resistance B16a and a capacitor B16b connected in series between the output node N13 of charge pump B13 and a ground node.
FIG. 26 is a circuit diagram showing a configuration of voltage controlling delay circuit B15 shown in FIG. 21.
With reference to FIG. 26, voltage controlling delay circuit B15 includes a bias generation circuit B21 and k delay time variable inverters B221-B22k (k is a natural number) connected in series.
Bias generation circuit B21 includes an N channel MOS transistor B21c having a gate receiving control voltage VCOin, a resistance B21r provided between a source of N channel MOS transistor B21c and the ground potential, a P channel MOS transistor B21a having a gate and a drain connected to a drain of N channel MOS transistor B21c and a source coupled with power supply potential Vcc, a P channel MOS transistor B21b having a gate receiving potential of the drain of N channel MOS transistor B21c and a source coupled with power supply potential Vcc and an N channel MOS transistor B21d having a drain and a gate connected to a drain of P channel MOS transistor B21b and a source coupled with the ground potential.
Potential of the drain of N channel MOS transistor B21c is at the level of a control potential Vp1 whereas potential of the drain of P channel MOS transistor B21b is at the level of a control potential Vn.
Delay time variable inverter B22k (k is a natural number) includes a P channel MOS transistor B22ak having a gate receiving control potential Vp1 and limiting a current from a power supply node to which power supply potential Vcc is applied, an N channel MOS transistor B22dk having a gate receiving the control potential Vn and limiting a current flowing to a ground node, and a P channel MOS transistor B22bk and an N channel MOS transistor B22ck connected in series between a drain of P channel MOS transistor B22ak and a drain of N channel MOS transistor B22dk. 
A gate of P channel MOS transistor B22bk and a gate of N channel MOS transistor B22ck are connected to form an input node of the delay time variable inverter whereas a drain of P channel MOS transistor B22bk forms an output node of the delay time variable inverter.
Next, an operation of voltage controlling delay circuit B15 shown in FIG. 26 will be described. As control voltage Vp1 is applied to all gates of P channel MOS transistors B22a1-B22ak and control voltage Vn is applied to all gates of N channel MOS transistors B22d1-B22dk, a current corresponding to control voltage VCOin flows to each of delay time variable inverters B221-B22k. With the increase in the control voltage VCOin, the current flow increases and shortens a delay time caused by inversion at the inverter whereby a delay time at voltage controlling delay circuit B15 is reduced. Conversely when the current flow decreases because of the decrease in control voltage VCOin, the delay time caused by inversion at each inverter and therefore the delay time at voltage controlling delay circuit B15 grows long.
Next is the description of an operation of the DLL circuit shown in FIG. 21.
When a phase of the clock signal RCLK lags behind that of the clock signal ECLK, phase comparator B12 supplies as outputs the control signal /UP having a pulse width corresponding to a phase difference between the clock signal ECLK and the clock signal RCLK and the control signal DOWN having a predetermined pulse width. Then by the operation of charge pump B13, control voltage VCOin which is the output of the loop filter increases and the delay time at voltage controlling delay circuit B15 decreases. Hence the phase of the clock signal RCLK advances and the phase difference between the clock signal ECLK and the clock signal RCLK becomes smaller.
Conversely when the phase of the clock signal RCLK leads that of the clock signal ECLK, phase comparator B12 supplies as outputs the control signal DOWN having a pulse width corresponding to the phase difference between the clock signal RCLK and the clock signal ECLK and the control signal /UP having a predetermined pulse width. Then correspondingly, charges are pulled out from loop filter B16 to charge pump B13. Thus control voltage VCOin is pulled down and the delay time of voltage controlling delay circuit B15 increases. Hence the phase of the clock signal RCLK is delayed and the phase difference between the clock signal RCLK and the clock signal ECLK becomes smaller.
After a repetition of this process, the phase of the clock signal RCLK is finally matched with the phase of the clock signal ECLK.
FIG. 27 illustrates waveforms of the external clock signal ext. CLK and the internal clock signal int. CLK shown in FIG. 21, referenced for describing the relation thereof.
As shown in FIG. 27, when there is no phase difference between the clock signal RCLK and the clock signal ECLK, clock buffer B14 supplies as an output the internal clock signal int. CLK having a phase advanced by a desired amount from that of the external clock signal ext. CLK.
The above described DLL circuit, however, is difficult to test to confirm its operation.
For example, in the DLL circuit, a frequency range of the external clock signal ext. CLK where the DLL circuit is normally operable is not infinite but finite. This frequency range is shifted because of fluctuation in performance caused in manufacturing semiconductor devices (process variation) and so on. For testing the shift in the frequency range, output voltage VCOin of loop filter B16 shown in FIG. 21 can be monitored. Here, however, the measurement with high precision is required and an error is inevitable to some extent.
An object of the present invention is to provide a semiconductor device including an internal clock generation circuit such as a DLL circuit, a PLL circuit or the like to which an operation confirmation test can easily be performed.
The present invention is, in brief, a semiconductor device including an internal clock generation circuit for generating an internal clock in synchronization with a reference clock and the semiconductor device includes a determination circuit. The internal clock generation circuit includes a delay line delaying a first clock generated according to the reference clock according to an n-bit (n: an integer of at least 2) control signal and supplying as an output the internal clock, a phase comparison circuit comparing phases of the internal clock and the reference clock, and a shift register supplying as an output the control signal according to result of comparison at the phase comparison circuit. The shift register shifts position of a transition bit in the control signal according to the result of comparison, when lower m bit (m: an integer at least 0 and at most n) among the n bits of the control signal has a first logic value and m+1 th bit to n th bit from the least significant bit has a second logic value, and a m th bit from the least significant bit is the transition bit. The determination circuit determines that a j th (j: an integer at least 0 and less than i) bit from the least significant bit of the control signal has the first logic value and a k th (k: an integer more than i and at most n) bit from the least significant bit of the control signal has the second logic value, assuming that the expected position of the transition bit is i th from the lowest position when the internal clock is normally generated, and supplies result as an output.
In accordance with another aspect of the present invention, the present invention is a semiconductor device including an internal clock generation circuit for generating an internal clock in synchronization with a reference clock, and the semiconductor device includes a first data terminal and a switching circuit. The internal clock generation circuit includes a first delay line for delaying a first clock generated according to the reference clock according to an n-bit (n: an integer at least 2) control signal and supplying as an output the internal clock, a phase comparison circuit comparing phases of the internal clock and the reference clock and a shift register supplying as an output the control signal according to result of comparison at the phase comparison circuit. The shift register shifts a position of a transition bit in the control signal according to the result of comparison when lower m bit (m: an integer at least 0 and at most n) among the n bits of the control signal has a first logical value and m+1 th bit to n th bit from the least significant bit has a second logical value, and a m th bit from the least significant bit is the transition bit. The first data terminal is employed for receiving/transmitting from/to an external source predetermined data at a normal operation. The switching circuit supplies as an output to the first data terminal the internal clock according to a test mode signal activated when an operation of the internal clock generation circuit is confirmed.
In accordance with still another aspect of the present invention, the present invention is a semiconductor device including an internal clock generation circuit for generating an internal clock in synchronization with a reference clock and the semiconductor device includes a phase determination circuit. The internal clock generation circuit includes a first delay line delaying a first clock generated according to the reference clock according to an n-bit (n: an integer at least 2) control signal and supplying as an output the internal clock, a second delay line delaying the first clock according to the control signal and supplying as an output a second clock, a phase comparison circuit comparing phases of the internal clock and the reference clock and a shift register supplying as an output the control signal according to result of comparison at the phase comparison circuit. The phase determination circuit determines whether phase difference between the internal clock and the first clock is at most a predetermined value or not.
Therefore a main advantage of the present invention lies in that the shift of the operating frequency range caused by the fluctuation of a delay time of a delay line because of the process variation can be easily detected by extraction and comparison of a portion of the control signal supplied as an output from the shift register included in the internal clock generation circuit.
Another advantage of the present invention lies in that the operation of the internal clock circuit can be easily and surely confirmed because a test mode is provided in which the internal clock generated from the internal clock generation circuit is directly supplied as an output.
Still another advantage of the present invention lies in that unsatisfactory behavior of the delay line which is difficult to detect can be detected because two delay lines with the identical configuration are provided and the test mode for comparing the outputs thereof is provided.